View MT29F2G08AAD_7727860.PDF datasheet online --- IC-ON-LINE

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products and specifications discussed herein ar e subject to change by micron without notice. 2gb x8, x16: nand flash memory features micron confidential and proprietary pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__1.fm - rev. a 8/08 en 1 ?2007 micron technology, inc. all rights reserved. nand flash memory MT29F2G08AAD, mt29f2g16aad, mt29f2g08abd, mt29f2g16abd features ? open nand flash interface (onfi) 1.0-compliant ? single-level cell (slc) technology ? organization ? page size: ? x8: 2,112 bytes (2,048 + 64 bytes) ? x16: 1,056 words (1,024 + 32 words) ? block size: 64 pages (128k + 4k bytes) ? device size: 2gb: 2,048 blocks ?read performance ? random read: 25s ? sequential read: 25ns (3.3v) ? sequential read: 35ns (1.8v) ?write performance ? program page: 220s (typ, 3.3v) ? program page: 300s (typ, 1.8v) ? block erase: 500s (typ) ? data retention: 10 years ? endurance: 100,000 program/erase cycles ? first block (block address 00h) guaranteed to be valid with ecc when shipped from factory 1 ? industry-standard basic nand flash command set ? advanced command set: ? program page cache mode ? page read cache mode ? one-time programmable (otp) commands ? block lock (1.8v only) ? programmable drive strength ? read unique id ? operation status byte provides a software method of detecting: ? operation completion ? pass/fail condition ? write-protect status ? ready/busy# (r/b#) signal provides a hardware method of detecting operation completion ? wp# signal: write protect entire device ? reset required as first command after power-up ? internal data move operations supported ? alternate method of device initialization (nand_init) after power up 4 (contact factory) figure 1: 63-ball vfbga 1. see ?error management? on page 61. 2. for part numbering and markings, see figure 2 on page 2 and figure 3 on page 3. 3. cpl = center parting line 4. available only in 1.8v vfbga package. options ?density 2 : 2gb (single die) ? device width: x8, x16 ? configuration: # of die # of ce# # of r/b# i/o 1 1 1 common ?v cc : 2.7?3.6v ?v cc : 1.65?1.95v ?package ? 48-pin tsop type i cpl 3 (lead-free plating, 3.3v only) ? 63-ball vfbga (lead-free, 1.8v only) ? operating temperature: ? commercial (0c to +70c) ? extended (?40c to +85c) free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__1.fm - rev. a 8/08 en 2 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory part numbering information micron confidential and proprietary part numbering information micron ? nand flash devices are available in several different configurations and densities (see figure 2). figure 2: part number chart (3.3v) mt 29f 2g 08 a a d wp es d micron technology product family 29f = single-supply nand flash memory density 2g = 2gb device width 08 = 8 bits 16 = 16 bits operating voltage range a = 3.3v (2.7C3.6v) feature set d = feature set d design revision d = fourth revision production status blank = production es = engineering sample ms = mechanical sample qs = qualification sample operating temperature range blank = commercial (0c to +70c) et = extended (C40c to +85c) reserved for future use blank flash performance blank = standard package code wp = 48-pin tsop cpl classification # of die # of ce# # of r/b# i/o a 1 1 1 common free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__1.fm - rev. a 8/08 en 3 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory part numbering information micron confidential and proprietary figure 3: part number chart (1.8v) valid part number combinations after building the part number from the part numbering chart, verify that the part number is offered and valid by using the micron parametric part search web site at www.micron.com/products/parametric . if the device required is not on this list, contact the factory. mt 29f 2g 08 a b d hc es :d micron technology product family 29f = single-supply nand flash memory density 2g = 2gb device width 08 = 8 bits 16 = 16 bits operating voltage range b = 1.8v (1.65C1.95v) feature set d = feature set d design revision d = fourth revision production status blank = production es = engineering sample ms = mechanical sample qs = qualification sample operating temperature range blank = commercial (0c to +70c) et = extended (C40c to +85c) reserved for future use blank flash performance blank = standard package code hc = 63-ball vfbga (lead-free) classification # of die # of ce# # of r/b# i/o a 1 1 1 common free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59atoc.fm - rev. a 8/08 en 4 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory table of contents micron confidential and proprietary table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 part numbering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 valid part number combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ready/busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 page read 00h-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 random data read 05h-e0h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 page read cache mode operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 read id 90h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 read unique id edh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 read parameter page ech . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 read status 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 program page 80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 serial data input 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 random data input 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 program page cache mode 80h-15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 internal data move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 read for internal data move 00h-35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 program for internal data move 85h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 block erase 60h-d0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 block lock feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 wp# and block lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 unlock 23h-24h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 lock 2ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 lock-tight 2ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 block lock read status 7ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 one-time programmable (otp) area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 otp data program a0h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 random data input 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 otp data protect a5h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 otp data read afh-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 features operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 get features eeh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 set features efh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 reset ffh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59atoc.fm - rev. a 8/08 en 5 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory table of contents micron confidential and proprietary write protect operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 v cc power cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59alof.fm - rev. a 8/08 en 6 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory list of figures micron confidential and proprietary list of figures figure 1: 63-ball vfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2: part number chart (3.3v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 3: part number chart (1.8v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 4: pin assignment 48-pin tsop type 1 cpl (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5: ball assignment: 63-ball vfbga (x 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6: ball assignment: 63-ball vfbga (x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7: nand flash functional block diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8: memory map (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9: memory map x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 10: array organization for mt29f2g 08axd (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11: array organization for mt29f2g 16axd (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 12: ready/busy# open drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 13: t fall and t rise (3.3v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14: t fall and t rise (1.8v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15: i ol vs. rp (3.3v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 16: i ol vs. rp (1.8v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 17: tc vs. rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 18: page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 19: random data read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 20: page read cache mode operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 21: read id operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 22: read unique id operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 23: read parameter page ech . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 24: status register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 25: program and read status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 26: random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 27: program page cache mo de example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 28: internal data move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 29: internal data move wi th optional random data output and random data input . 39 figure 30: block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 31: flash array protected: inverted area bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 32: flash array protected: invert area bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 33: unlock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 34: lock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 35: lock-tight operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 36: program/erase issued to locked block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 37: block lock read status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 38: block lock flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 39: otp data program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 40: otp program with random data in put . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 41: otp data protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 42: otp data read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 43: otp data read with random data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 44: get features (eeh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 45: set features (efh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 46: reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 47: erase enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 48: erase disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 49: program enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 50: program disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 51: program for internal data move enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 52: program for internal data move disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 53: ac waveforms during power transi tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 54: command latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 55: address latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 56: input data latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59alof.fm - rev. a 8/08 en 7 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory list of figures micron confidential and proprietary figure 57: serial access cycle after read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 58: serial access cycle after read (edo mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 59: read status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 60: page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 61: read operation with ce# ?don?t care? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 62: random data read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 63: page read cache mode operation, part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 64: page read cache mode operation, part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 65: page read cache mode operation without r/b#, part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 66: page read cache mode operation without r/b#, part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 67: read id operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 68: program page operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 69: program op eration with ce# ?don?t care? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 70: program page operation with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 71: internal data move operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 72: program page cache mode operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 73: program page cache mode operat ion ending on 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 74: block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 75: reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 76: 48-pin tsop package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 77: 63-ball vfbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59alot.fm - rev. a 8/08 en 8 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory list of tables micron confidential and proprietary list of tables table 1: signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2: operational example (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3: operational example (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4: array addressing: mt29f2g08axd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5: array addressing: mt29f2g16axd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6: mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7: command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8: block-lock command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9: device id and configuration codes for address 00h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 10: device id and configuration codes for address 20h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 11: onfi parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12: status register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 13: block lock address cycle assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 14: block lock status register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 15: features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 16: feature address 01h: timing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 17: feature address 80h: programmable i/o drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 18: feature address 81h: programmable r/b# pull-down streng th . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 19: status register contents after re set operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 20: error management details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 21: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 22: recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 23: dc and operating characteristics (3.3v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 24: dc and operating characteristics (1.8v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 25: valid blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 26: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 27: test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 28: ac characteristics: command, data, and address input (3 .3v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 29: ac characteristics: command, data, and address input (1 .8 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 30: ac characteristics: normal operat ion (3.3v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 31: ac characteristics: normal operat ion (1.8v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 32: program/erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 9 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory general description micron confidential and proprietary general description nand flash technology provides a cost-effec tive solution for applications requiring high-density, solid-state storage. the mt 29f2gxxaxd is a 2gb nand flash memory device. micron nand flash devices include st andard nand flash fe atures as well as new features designed to enhance system-level performance. micron nand flash devices use a highly multiplexed 8-bit bus (i/o[7:0]) to transfer data, addresses, and instructions. the five command pins (cle, ale, ce#, re#, we#) implement the nand flash command bus inte rface protocol. additi onal pins control hardware write protection (wp#), monitor the device ready/busy (r/b#) state, and enable block lock functionality (lock). this hardware interface creates a low-pin-coun t device with a standard pinout that is the same from one density to another, allowing future upgrades to higher densities with- out board redesign. the mt29f2g device contains 2,048 blocks. ea ch block is subdivided into 64 program- mable pages. each page consists of 2,112 by tes. the pages are further divided into a 2,048-byte data storage region with a separate 64-byte area. the 64-byte area is typically used for error management functions. the contents of each page can be programme d in tprog (typ), and an entire block can be erased in tbers (typ). on-chip contro l logic automates program and erase oper- ations to maximize cycle endurance. program/erase endurance is specified at 100,000 cycles using appropriate error corr ection code (ecc) and error management. figure 4: pin assignment 48-pin tsop type 1 cpl (top view) notes: 1. for package dimensions , see figure 91 on page 99. 2. these pins might not be bond ed in the package. however, micron recommends that the customer connect these pins to the designated external so urces for onfi compatibility. x8 nc nc nc nc nc nc r/b# re# ce# nc nc vcc vss nc nc cle ale we# wp# nc dnu dnu nc nc x16 nc nc nc nc nc nc r/b# re# ce# nc nc vcc vss nc nc cle ale we# wp# nc dnu dnu nc nc x8 vss 2 nc nc nc i/o7 i/o6 i/o5 i/o4 nc vcc 2 dnu vcc vss nc vcc 2 nc i/o3 i/o2 i/o1 i/o0 nc nc nc vss 2 x16 vss i/o15 i/o14 i/o13 i/o7 i/o6 i/o5 i/o4 i/o12 vcc dnu vcc vss nc vcc i/o11 i/o3 i/o2 i/o1 i/o0 i/o10 i/o9 i/o8 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 10 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory general description micron confidential and proprietary figure 5: ball assignment: 63-ball vfbga (x8) notes: 1. for package dimensio ns, see figure 77 on page 87 2. these pins might not be bond ed in the package. however, micron recommends that the customer connect these pins to the designated external so urces for onfi compatibility. 3 wp# vcc 2 nc nc dnu nc nc vss 1 nc nc nc nc a b c d e f g h j k l m 2 nc nc nc 4 ale re# nc nc vcc 2 i/o0 i/o1 i/o2 8 r/b# nc nc nc nc vcc i/o7 vss 10 nc nc nc nc 9 nc nc nc nc 5 vss cle nc nc lock nc nc i/o3 7 we# nc nc vss 2 nc nc i/o5 i/o6 6 ce# nc nc nc nc nc vcc i/o4 top view, ball down free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 11 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory general description micron confidential and proprietary figure 6: ball assignment: 63-ball vfbga (x16) notes: 1. for package dimensions, see figure 77 on page 87. 3 wp# vcc nc nc dnu i/o8 i/o9 vss 4 ale re# nc nc vcc i/o0 i/o1 i/o2 8 r/b# nc nc nc nc vcc i/o7 vss 10 nc nc nc nc 9 nc nc nc nc 5 vss cle nc nc lock i/o10 i/o11 i/o3 7 we# nc nc vss i/o15 i/o14 i/o5 i/o6 6 ce# nc nc nc i/o13 i/o12 vcc i/o4 top view, ball down 1 nc nc nc nc a b c d e f g h j k l m 2 nc nc nc free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 12 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory general description micron confidential and proprietary table 1: signal descriptions symbol type description ale input address latch enable: duri ng the time ale is high, address information is transferred from i/o[7:0] into the on-chip address registe r on the rising edge of we# . when address information is not bein g loaded, ale should be driven low. ce# input chip enable: this gates transfers betw een the host system and the nand flash device. after the device starts a progra m or erase operation, ce# can be de- asserted. see ?bus operation? on page 18 for additional operational details. cle input command latch enable: when cle is hi gh, information is transferred from i/o[7:0] to the on-chip co mmand register on the rising edge of we#. when command information is not being loaded, cle should be driven low. lock input when lock is high during power-up, the block lock function is enabled. to disable the block lock, connect lock to v ss during power-up, or leave it disconnected (internal pull-down). re# input read enable: this gates transfers from the nand flash device to the host system. we# input write enable: this gates transfers from the host system to the nand flash device. wp# input write protect: this protects against in advertent program and erase operations. all program and erase operations are disabled when wp# is low. i/o[7:0] (x8) i/o[15:0] (x16) i/o data inputs/outputs: the bi directional i/os transfer address, data, and instruction information. data is output only during read operations; at other times the i/os are inputs. r/b# output ready/busy: this is an open-drain , active-low output that uses an external pull- up resistor. r/b# is used to indicate when the chip is processing a program or erase operation. it is also used during re ad operations to indicate when data is being transferred from the array into th e serial data register. when these operations have completed, r/b# returns to the high-impedance state. v cc supply v cc : this is the power supply. v ss supply v ss : this is the ground connection. nc ? no connect: ncs are not in ternally connected. they can be driven or left unconnected. dnu ? do not use: dnus must be left unconnected. free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 13 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory architecture micron confidential and proprietary architecture these devices use nand flash electrical and command interfaces. data, commands, and addresses are multiplexed onto the same pins and received by i/o control circuits. this provides a memory device with a low pin count. the commands received at the i/o control circuits are latched by a command register and are transferred to control logic circuits for generating internal signals to control device operations. the addresses are latched by an address register and sent to a row decoder or a column decoder to select a row address or a column address, respectively. the data are transferred to or from the nand flash memory array, byte by byte (x8) or word by word (x16), through a data register and a cache register. the cache register is closest to i/o control circuits and acts as a data buffer for the i/o data, whereas the data register is closest to the memory array an d acts as a data buffe r for the nand flash memory array operation. the nand flash memory array is programmed and read in page-based operations and is erased in block-based operations. during normal page operations, the data and cache registers are tied together and act as a single register. during cache operations the data and cache registers operate independen tly to increase data throughput. these devices also have a status register th at reports the status of device operation. figure 7: nand flash functional block diagram notes: 1. lock pin is used for 1.8v device. address register data register cache register status register command register ce# v cc v ss cle ale we# re# wp# lock 1 i/ox control logic i/o control r/b# row decode column decode nand flash array free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 14 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory addressing micron confidential and proprietary addressing nand flash devices do not contain dedicate d address pins. addresses are loaded using a 5-cycle sequence as shown in tables 4 and 5, on pages 16 and 17. see figure 8 for addi- tional memory mapping and addressing details. memory mapping figure 8: memory map (x8) notes: 1. as shown in table 4 on page 16, the high nibble of address cycle 2 has no assigned address bits; however, these 4 bits must be held low during the addr ess cycle to ensure that the address is interpreted correctly by the nand flash device. these extra bits are accounted for in address cycle 2 even though they do not ha ve address bits assigned to them. 2. the 12-bit column address is capable of addres sing from 0 to 2,047 bytes on a x8 device; however, only bytes 0 through 2,111 are valid . bytes 2,112 through 4,095 of each page are ?out of bounds,? do not exist in the device, and cannot be addressed. table 2: operational example (x8) block page min address in page max address in page out of bounds addresses in page 0 0 0x0000000000 0x000000083f 0x0000000840?0x0000000fff 0 1 0x0000010000 0x000001083f 0x0000010840?0x0000010fff 0 2 0x0000020000 0x000002083f 0x0000020840?0x0000020fff ?? ? ? 2,046 62 0x01fffe0000 0x01fffe083f 0x01fffe0840?0x01fffe0fff 2,047 63 0x01ffff0000 0x01ffff 083f 0x01ffff0840?0x01ffff0fff ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? blocks 2gb: ba[16:6] pages pa[5:0] bytes ca[11:0] 012 012 63 0 1 2 2,047 ? ? ? 2,111 2,047 spare area free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 15 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory memory mapping micron confidential and proprietary figure 9: memory map x16 notes: 1. as shown in table 5 on page 17, the uppe r 5 bits of address cycl e 2 have no assigned address bits; however, these 5 bits must be held low during the addr ess cycle to ensure that the address is interpreted correctly by the nand flash device. these extra bits are accounted for in address cycle 2 even though they do not ha ve address bits assigned to them. 2. the 11-bit column address is capable of addres sing from 0 to 2,047 words on x16 devices; however, only words 0 throug h 1,055 are valid. words 1,056 through 2,048 of each page are ?out of bounds,? do not exist in the device, and cannot be addressed. table 3: operational example (x16) block page min address in page max address in page out of bounds addresses in page 0 0 0x0000000000 0x000000041f 0x0000000420?0x0000000fff 0 1 0x0000010000 0x000001041f 0x0000010420?0x0000010fff 0 2 0x0000020000 0x000002041f 0x0000020420?0x0000020fff ?? ? ? 2,046 62 0x01fffe0000 0x01fffe041f 0x01fffe0420?0x01fffe0fff 2,047 63 0x01ffff0000 0x01ffff041f 0x01ffff0420?0x01ffff0fff ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? blocks ba[16:6] pages pa[5:0] words ca[10:0] 012 012 63 0 1 2 1,023 ? ? ? 1,055 2,047 spare area free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 16 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory array organization micron confidential and proprietary array organization figure 10: array organization for mt29f2g08axd (x8) notes: 1. if ca11 is ?1,? th en ca[10:6] must be ?0.? 2. block address concatenated with page address = actual page address; cax = column address; pax = page address; bax = block address. table 4: array addressing: mt29f2g08axd cycle i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second lowlowlowlowca11 1 ca10 ca9 ca8 third ba7 ba6 pa5 pa4 pa3 pa2 pa1 pa0 fourth ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 fifth low low low low low low low ba16 cache register data register 2,048 blocks per device 1 block 64 2,048 64 2,048 2,112 bytes i/o 7 i/o 0 64 pages = 1 block (128k + 4k) bytes 1 page = (2k + 64) bytes 1 block = (2k + 64) bytes x 64 pages = (128k + 4k) bytes 1 device = (2k + 64) bytes x 64 pages x 2,048 blocks = 2,112mb free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 17 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory array organization micron confidential and proprietary figure 11: array organization for mt29f2g16axd (x16) notes: 1. if ca10 is ?1,? then ca[9:5] must be ?0.? 2. block address concatenated with page address = actual page address. cax = column address; pax = page address; bax = block address. 3. i/o[15:8] are not used during the addre ssing sequence and should be driven low. table 5: array addressing: mt29f2g16axd cycle i/o[15:8] i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first low ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second low low low low low low ca10 1 ca9 ca8 third low ba7 ba6 pa5 pa4 pa3 pa2 pa1 pa0 fourth lowba15ba14ba13ba12ba11ba10 ba9 ba8 fifth low low low low low low low low ba16 cache register data register 2,048 blocks per device 1 block 32 1,024 32 1,024 1,056 words i/o 15 i/o 0 64 pages = 1 block (64k + 2k) words 1 page = (1k + 32) words 1 block = (1k + 32) words x 64 pages = (64k + 2k) words 1 device = (1k + 32) words x 64 pages x 2,048 blocks = 2,112mb free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 18 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory bus operation micron confidential and proprietary bus operation the bus on the mt29fxxx devices is multip lexed. data i/o, addresses, and commands all share the same pins. i/o[15:8] are used only for data in the x16 configuration. addresses and commands are always supplied on i/o[7:0]. the command sequence normally consists of a command latch cycle, address input cycles, and one or more data cycles?either read or write. control signals ce#, we#, re#, cle, ale and wp# control nand flash device read and write opera- tions. ce# is used to enable the device. when ce# is low and the device is not in the busy state, the nand flash memory will accept command, address, and data information. when the device is not performing an operat ion, the ce# pin is typically driven high and the device enters standby mode. the memory will enter standby if ce# goes high while data is being transferred and the device is not busy. this helps reduce power con- sumption. see figure 61 on page 75 and figure 69 on page 81 for examples of ce# ?don?t care? operations. the ce# ?don?t care? operation enables the nand flash to reside on the same asyn- chronous memory bus as other flash or sram devices. other devices on the memory bus can then be accessed while the nand flas h is busy with internal operations. this capability is important for designs that re quire multiple nand flash devices on the same bus. a high cle signal indicates th at a command cycle is taking place. a high ale signal signifies that an address input cycle is occurring. commands commands are written to the command register on the rising edge of we# when: ? ce# and ale are low, and ?cle is high, and ? the device is not busy as exceptions, the device accepts the read status and reset commands when busy. commands are transferred to the command register on the rising edge of we# (see figure 54 on page 71). commands are input on i/o[7:0] only. for devi ces with a x16 interface, i/o[15:8] must be written with zeros when a command is issued. address input addresses are written to the address register on the rising edge of we# when: ? ce# and cle are low, and ?ale is high addresses are input on i/o[7:0]. bits not part of the address space must be low. for devices with a x16 interface, i/o[15:8] must be written with zeros when an address is issued (see figure 55 on page 71). the number of address cycles required for each command varies. refer to the com- mand descriptions to determine addressing requirements (see table 7 on page 24). free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 19 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory bus operation micron confidential and proprietary data input data is written to the data register on the rising edge of we# when: ? ce#, cle, and ale are low, and ? the device is not busy data is input on i/o[7:0] on x8 devices and on i/o[15:0] on x16 devices. see figure 56 on page 72 for additional data input details. reads after a read command is issued, data is tran sferred from the memory array to the data register on the rising edge of we#. r/b# goes low for t r and transitions high after the transfer is complete. when data is available in the data register, it is clocked out of the part by re# going low. see figure 60 on page 74 for detailed timing information. the read status (70h) command or the r/b# signal can be used to determine when the device is ready. if a controller is using a timing of 30ns or longer for t rc, use figure 57 on page 72 for proper timing. ready/busy# the r/b# output provides a hardware meth od of indicating th e completion of pro- gram, erase, and read operations. the signal requires a pull-up resistor for proper operation. the signal is typically high, an d transitions to low after the appropriate command is written to the device. the signal pin?s open-drain driver enables multiple r/b# outputs to be or-tied. the read status command can be used in place of r/b#. typically, r/b# is connected to an interrupt pin on the system controller (see figure 12 on page 20 ). the combination of rp and capacitive loadin g of the r/b# circuit determines the rise time of the r/b# pin. the actual value used for rp depends on the system timing requirements. large values of rp cause r/b# to be delayed significantly. at the 10- to 90-percent points on the r/b# waveform, rise time is approximately two time constants (tc). the fall time of the r/b# signal is determ ined mainly by the output impedance of the r/b# pin and the total load capacitance and may be changed if r/b pull-down strength is not set to ?full.? figure 15 on page 21 and figures 16 and 17 on page 22 depict approximate rp values using a circuit load of 100pf. tc r c = where r = rp (resistance of pull-up resistor), and c = total capacitive load. free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 20 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory bus operation micron confidential and proprietary the minimum value for rp is determined by th e output drive capability of the r/b# sig- nal, the output voltage swing, and v cc . figure 12: ready/busy# open drain figure 13: t fall and t rise (3.3v) notes: 1. t fall and t rise calculated at 10 percent and 90 percent points. 2. t rise is primarily dependent on external pull -up resistor and extern al capacitive loading. 3. t fall 7ns at 1.8v. 4. see tc values in figure 17 on page 22 for approximate rp value and tc. rp min, 1.8v part () v cc max () v ol max () ? i ol i l + --------------------------------------------------------------- = 1.85 v 3 ma i l + -------------------------- - = where i l is the sum of the input currents of all devices tied to the r/b# pin. rp r/b# open drain output v cc gnd device i ol 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 -1 0 2 4 0 2 4 6 t fall t rise vcc 3.3 tc v free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 21 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory bus operation micron confidential and proprietary figure 14: t fall and t rise (1.8v) notes: 1. t fall and t rise calculated at 10 percent and 90 percent points. 2. t rise is primarily dependent on external pull -up resistor and extern al capacitive loading. 3. t fall 7ns at 1.8v. 4. see tc values in figure 17 on page 22 for approximate rp value and tc. figure 15: i ol vs. rp (3.3v) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 -1 0 2 4 0 2 4 6 t fall t rise v cc 1.8 tc v 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 2,000 4,000 6,000 8,000 10,000 12,000 rp ( : ) t (s) i ol at 3.6v (ma) free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 22 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory bus operation micron confidential and proprietary figure 16: i ol vs. rp (1.8v) figure 17: tc vs. rp 3.50ma 3.00ma 2.50ma 2.00ma 1.50ma 1.00ma 0.50ma 0.00ma 0 2,000 4,000 6,000 8,000 10,000 12,000 i ol at 1.95v (max) rp ( : ) i 1.20s 1.00s 800ns 600ns 400ns 200ns 0ns 0 2,000 4,000 6,000 8,000 10,000 12,000 i ol at v cc (max) rc = tc c = 100pf rp ( : ) t free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 23 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory bus operation micron confidential and proprietary notes: 1. wp# should be biased to cmos high or low for standby. 2. mode selection settings for this table: h = logic level high; l = logic level low; x = v ih or v il . table 6: mode selection cle ale ce# we# re# wp# lock 3 mode hll hxx read mode command input lhl hxx address input hll hhx write mode command input lhl hhx address input lll hhx data input lllh xx sequential read and data output xxxhhxx during read (busy) xxxxxhx during program (busy) xxxxxhx during erase (busy) xxxxxlx write protect xxhxx0v/v cc 1 x standby free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 24 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary command definitions notes: 1. indicates required data cycles be tween command cycle 1 and command cycle 2. 2. random data read command limite d to use within a single page. 3. random data input command limite d to use within a single page. table 7: command set command command cycle 1 number of address cycles data cycles required 1 command cycle 2 valid during busy notes page read 00h 5 no 30h no page read cache mode random 00h 5 no 31h no page read cache mode sequential 31h ? no ? no page read cache mode last 3fh ? no ? no read for internal data move 00h 5 no 35h no random data read 05h 2 no e0h no 2 read id 90h 1 no ? no read unique id edh 1 no ? no read parameter page ech 1 no ? no read status 70h ? no ? yes program page 80h 5 yes 10h no program page cache mode 80h 5 yes 15h no program for internal data move 85h 5 optional 10h no random data input 85h 2 yes ? no 3 block erase 60h 3 no d0h no reset ffh ? no ? yes otp data program a0h 5 yes 10h no otp data protect a5h 5 no 10h no otp data read afh 5 no 30h no get features eeh 1 no ? no set features efh 1 4 ? no table 8: block-lock command set command command cycle 1 number of address cycles command cycle 2 number of address cycles valid during busy unlock 23h 3 24h 3 no block lock 2ah ? ? ? no block lock-tight 2ch ? ? ? no block lock read status 7ah 3 ? ? no free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 25 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary read operations page read 00h-30h at power-on, the device defaults to read mode. to enter read mode while in opera- tion, write the 00h command to the command register, then write 5 address cycles, and conclude with the 30h command. to determine the progress of the data transfer from the nand flash array to the data register ( t r), monitor the r/b# signal; or alternatively, issue a read status (70h) com- mand. if the read status command is used to monitor the data transfer, the user must reissue the read (00h) command to receive data output from the data register. see figure 65 on page 79 and figure 66 on page 80 for examples. after the read command has been reissued, pulsing the re# line will re sult in outputting data, starting from the initial column address. a serial page read sequence outputs a complete page of data. after 30h is written, the page data is transferred to the data regist er, and r/b# goes low during the transfer. when the transfer to the data register is complete, r/b# returns high. at this point, data can be read from the device. starting from the initial column address to the end of the page, read the data by repeatedly pulsing re# at the maximum t rc rate (see figure 18). figure 18: page read operation re# ce# ale cle i/ox 00h address (5 cycles) data output (serial access) 30h r/b# we# t r dont care free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 26 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary random data read 05h-e0h the random data read command enables the user to specify a new column address so the data at single or multiple addresses can be read. the random read mode is enabled after a normal page read (00h-30h) sequence. random data can be output after the initial page read by writing an 05h-e0h command sequence along with the new column address (2 cycles). the random data read command can be issued without limit within the page. only data on the current page can be read. pulsing the re# pin outputs data sequentially (see figure 19). figure 19: random data read operation page read cache mode operations micron nand flash devices have a cache register that can be used to increase the read operation speed. data can be output from the device's cache register while a page is concurrently moved from the nand flash array to the data register. to begin a page read cache mode command sequence, issue the page read (00h- 30h) command to read a page from the nand flash array to the cache register. r/b# goes low during t r (status register bits 6 and 5 = 00). after t r (r/b# is high and status register bits 6 and 5 = 11), issue either: ? the page read cache mode sequential (31h) command to begin copying the next sequential page from the nand flash array to the data register, or ? the page read cache mode random (00h-31h) command to begin copying the page specified in this command from the nand flash array to the data register. after the page read cache mode sequential or page read cache mode ran- dom command has been issued, r/b# goes low (status register bits 6 and 5 = 00) for t dcbsyr1 while the device begins to copy th e next page into the data register. after t dcbsyr1, r/b# goes high and status regist er bits 6 and 5 = 10, indicating that the cache register is available. at this point, data can be output from the cache register by toggling re# beginning at column address 0. the random data read (05h-e0h) com- mand can be used to change the column addr ess of the data being output by the device. after the desired number of bytes are output from the cache register, it is possible to either begin an additional page read ca che mode (31h or 00h-31h) operation or issue the page read cache mode last (3fh) command. if an additional page read cache mode ( 31h or 00h-31h) operation is issued, r/b# goes low (status register bits 6 and 5 = 00) for t dcbsyr2 while the data register is cop- ied to the cache register and the device begins to copy the next page into the data regis- ter. after t dcbsyr2, r/b# goes high and status register bits 6 and 5 = 10, indicating that re# i/ox 00h address (5 cycles) data output data output 30h 05h address (2 cycles) e0h r/b# t r free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 27 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary the cache register is available. at this point, data can be output from the cache register by toggling re# beginning at column address 0. the random data read (05h-e0h) command can be used to change the column address of the data being output by the device. if the page read cache mode last (3fh) command is issued, r/b# goes low (status register bits 6 and 5 = 00) for t dcbsyr2 while the data register is copied into the cache register. after t dcbsyr2, r/b# goes high and status re gister bits 6 and 5 = 11, indicating that the cache register is available and that the nand flash array is ready for another command. at this point, data can be output from the cache register by toggling re# beginning at column address 0. the random data read (05h-e0h) command can be used to change the column address of the data being output by the device. during busy times ( t dcbsyr1 and t dcbsyr2), the only valid commands are read sta- tus (70h) and reset (ffh). until status register bit 5 = 1, the only valid commands dur- ing page read cache mode operations are read status (70h), page read cache mode (31h and 00h-31h), random data read (05h-e0h), and reset (ffh). page read cache mode sequential 31h the page read cache mode sequential (31h) command reads the next sequential page within a block into the data register wh ile the previous page is output from the cache register. to issue this command, write 31h to the command register. when this command is issued, r/b# goes lo w (status register bits 6 and 5 = 00) for either t dcbsyr1 or t dcbsyr2. after t dcbsyr1 or t dcbsyr2, r/b# goes high and sta- tus register bits 6 and 5 = 10, indicating that the cache register is available. at this point, data can be output from the cache register by toggling re# beginning at column address 0. the random data read (05h-e0h) command can be used to change the column address of the data being output by the device. page read cache mode random 00h-31h the page read cache mode random (00h-31h) command reads the specified page into the data register while the previous page is output from the cache register. to issue this command, write 00h to the command register. then write 5 address cycles to the address register. conclude the sequence by writing 31h to the command register. the column address in the address specified is ignored. when this command is issued, r/b# goes lo w (status register bits 6 and 5 = 00) for either t dcbsyr1 or t dcbsyr2. after t dcbsyr1 or t dcbsyr2, r/b# goes high and sta- tus register bits 6 and 5 = 10, indicating that the cache register is available. at this point, data can be output from the cache register by toggling re# beginning at column address 0. the random data read (05h-e0h) command can be used to change the column address of the data being output by the device. page read cache mode last 3fh the page read cache mode last (3fh) command copies a page from the data regis- ter to the cache register without beginning a new cache read. to issue this command, write 3fh to the command register. when this command is issued, r/b# goes lo w (status register bits 6 and 5 = 00) for t dcbsyr2. after t dcbsyr2, r/b# goes high and status register bits 6 and 5 = 11, indi- cating that the cache register is available and that the nand flash array is ready for another command. at this point, data can be output from the cache register by toggling re# beginning at column address 0. the random data read (05h-e0h) command can be used to change the column address of the data being output by the device. free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 28 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary figure 20: page read cache mode operations re# ce# ale cle i/ox 00h address (5 cycles) data output 31h 30h r/b# we# t r t dcbsyr1 re# ce# ale cle i/ox r/b# we# t dcbsyr2 t dcbsyr2 data output 3fh data output address (5 cycles) 00h 31h 1 1 page read cache mode random operation repeat as many times as necessary repeat as many times as necessary page read cache mode sequential operation free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 29 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary read id 90h the read id command is used to read the 5 bytes of identifier code programmed into the nand flash devices. the read id command reads a 5-byte table that includes manufacturer id, device configuration, and part-specific information (see table 9 on page 30). writing 90h to the command register puts the device into the read id mode. the com- mand register stays in this mode until the next command cycle is issued (see figure 21 ). figure 21: read id operation note: see table 9 on page 30 for byte definitions. we# ce# ale cle re# i/ox 90h 00h (or 20h) address, 1 cycle byte 2 byte 0 byte 1 byte 3 byte 4 t ar t rea t whr free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 30 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary notes: 1. b = binary; h = hex. table 9: device id and configuration codes for address 00h address = 00h options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value 1 byte 0 manufacturer id micron 001011002ch byte 1 device id mt29fg08aad 2gb, x8, 3v 11011010dah mt29f2g16aad 2gb, x16, 3v 1 1 0 0 1 0 1 0 cah mt29f2g08abd 2gb, x8, 1.8v 10101010aah mt29f2g16abd 2gb, x16, 1.8v 1 0 1 1 1 0 1 0 bah byte 2 number of die per ce 1 0 000b cell type slc 0 000b number of simultaneously programmed pages 1 0 001b interleaved operations between multiple die not supported 00b cache programming supported 11b byte value mt29f2gxxxxx 1 0 0 0 0 0 0 0 80h byte 3 page size 2kb 0 101b spare area size (bytes) 64b 11b block size (w/o spare) 128kb 0 1 01b organization x8 00b x16 11b serial access (min) 25ns 1 0 1xxxb serial access (min) 35ns 0 0 0xxx0b byte value MT29F2G08AAD 1 0 0 1 0 1 0 1 95h mt29f2g16aad 1 1 0 1 0 1 0 1 d5h byte value mt29f2g08abd 0 0 0 1 0 1 0 1 15h mt29f2g16abd 0 1 0 1 0 1 0 1 55h byte 4 reserved 0 000b planes per ce# 1 0 000b plane size 2gb 1 0 1 101b reserved 00b byte value mt29f2gxx 0101000050h table 10: device id and configuration codes for address 20h address = 20h options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value notes byte 0 ?o? 010011114fh byte 1 ?n? 010011104eh byte 2 ?f? 0100011046h byte 3 ?i? 0100100149h byte 4 undefinedxxxxxxxxxxh free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 31 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary read unique id edh micron offers the read unique id command to provide a method for uniquely identi- fying a nand flash device. the read unique id operation uses stan dard command and address timing. the for- mat of the id is arbitrary; however, this id is guaranteed to be unique for every nand flash device manufactured. many controllers use proprietary error correc tion code (ecc) schemes; thus, it is not possible for micron to protect unique id data with fa ctory-programmed ecc. however, to ensure data integrity, micron programs the noted nand flash devices with a 16-byte unique id, beginning at byte 0 of the page, then follows with 16 bytes of complement id. these 32 bytes of data are then repeated a total of 16 times, such that the last byte of the last copy of complement unique id resides at byte 511 in the page. the user can simply xor the first copy of the unique id and its comp lement. if the result is ?1,? the unique id is good. in the unlikely event that the resu lt is non-zero, the user can repeat the xor operation on a subsequent copy of the uniq ue id data. figure 22 shows timing for the device. the upper eight i/os on an x16 device ar e not used and are a ?don?t care? for x16 devices. figure 22: read unique id operation we# ale cle re# r/b# edh 00h t r byte 0 byte 1 byte 14 unique id data byte 15 i/o[7:0] free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 32 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary read parameter page ech the read parameter page function retrieves the data structure that describes the device's organization, featur es, timings, and other behavioral parameters. the data structure is repeated at least three times. figure 23 defines the read parameter page behavior. the random data read (05h-e0h) command is permitted during data output. the upper eight i/os on an x16 device ar e not used and are a ?don?t care? for x16 devices. figure 23: read parameter page ech table 11: onfi parameters byte description value 0?3 parameter page signature 4fh, 4eh, 46h, 49h 4?5 revision number 02h, 00h 6-7 features supported MT29F2G08AAD 10h, 00h mt29f2g16aad 11h, 00h mt29f2g08abd 10h, 00h mt29f2g16abd 11h, 00h 8-9 optional commands supported 3fh, 00h 10?31 reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h , 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h , 00h, 00h, 00h 32?43 device manufacturer 4dh, 49h, 43h, 52h, 4fh, 4eh, 20h, 20h, 20h, 20h, 20h, 20h 44?63 device model MT29F2G08AAD 4dh, 54h, 32h, 39h, 46 h, 32h, 47h, 30h, 38h, 41 h, 41h, 44h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h mt29f2g16aad 4dh, 54h, 32h, 39h, 46h, 32h, 47h, 31h, 36h, 41h, 41h, 44h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h mt29f2g08abd 4dh, 54h, 32h, 39h , 46h, 32h, 47h, 30h, 38h, 41h, 42h, 44h , 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h mt29f2g16abd 4dh, 54h, 32h, 39h , 46h, 32h, 47h, 31h, 36h, 41h, 42h, 44h , 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h 64 manufacturer id 2ch 65?66 date code 00h,00h 67?79 reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 80?83 number of data bytes per page 00h, 08h, 00h, 00h we# ale cle re# r/b# ech 00h t r p0 p1 p1022 p1023 i/o[7:0] free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 33 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary 84?85 number of spare bytes per page 40h, 00h 86?89 number of data bytes per partial page 00h, 02h, 00h, 00h 90?91 number of spare bytes per partial page 10h, 00h 92?95 number of pages per block 40h, 00h, 00h, 00h 96-99 number of blocks per unit 00h, 08h, 00h, 00h 100 number of logical units 01h 101 number of address cycles 23h 102 number of bits per cell 01h 103?104 bad blocks maximum per unit 28h, 00h 105?106 block endurance 01h, 05h 107 guaranteed valid blocks at beginning of target 01h 108?109 block enduranc e for guaranteed valid blocks 00h, 00h 110 number of programs per page 04h 111 partial programming attributes 00h 112 number of ecc bits 01h 113 number of interl eaved address bits 00h 114 interleaved operation attributes 00h 115?127 reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 128 i/o pin capacitance 0ah 129?130 timing mode support MT29F2G08AAD 1fh, 00h mt29f2g16aad 1fh, 00h mt29f2g08abd 07h, 00h mt29f2g16abd 07h, 00h 131?132 program cache timing MT29F2G08AAD 1fh, 00h mt29f2g16aad 1fh, 00h mt29f2g08abd 07h, 00h mt29f2g16abd 07h, 00h 133?134 t prog maximum page program time MT29F2G08AAD f4h, 01h mt29f2g16aad f4h, 01h mt29f2g08abd bch, 02h mt29f2g16abd bch, 02h 135?136 t bers maximum block erase time b8h, 0bh 137?138 t r maximum page read time 19h, 00h 139?140 t ccs minimum MT29F2G08AAD 46h, 00h mt29f2g16aad 46h, 00h mt29f2g08abd 64h, 00h mt29f2g16abd 64h, 00h 141?163 reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h , 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00 h, 00h, 00h, 00h, 00h 164?165 vendor-specific revision number 01h, 00h table 11: onfi parameters (continued) byte description value free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 34 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary read status 70h these nand flash devices have an 8-bit status register the software can read during device operation. on the x16 device, i/o[15:8] are ?0? when the status register is being read. table 12 describes the status register. after a read status command, all read cycles will be from the status register until a new command is issued. changes in the status register will be seen on i/o[7:0] as long as ce# and re# are low; it is not necessary to start a new read status cycle to see these changes. while monitoring the status register to determine when the t r (transfer from nand flash array to data register) is complete, the user must reissue the read (00h) command to make the change from status to read mode. after the read command has been re- issued, pulsing the re# line will result in ou tputting data, starting from the initial col- umn address. notes: 1. status register bit 5 is ?0? during the actual programming operation. if cache mode is used, this bit will be ?1? when al l internal operatio ns are complete. 2. status register bit 6 is ?1? wh en the cache is ready to accept new data. r/b# follows bit 6. see figure 27 on page 37 and figure 73 on page 84. 166?253 vendor specific 00h, 00h, 00h, 02h, 04h, 80h, 01h, 81h, 04h, 01h, 02h, 01h, 0ah, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00 h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00 h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00 h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00 h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00 h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 254?255 integrity crc set at test. 256?511 value of bytes 0?255 512?767 value of bytes 0?255 768+ additional redundant parameter pages table 12: status register bit definition sr bit program page program page cache mode page read page read cache mode block erase definition 0 pass/fail pass/fail (n) ? ? pass/fail 0 = successful program/erase 1 = error in program/erase 1 ? pass/fail (n-1) ? ? ? 0 = successful program 1 = error in program 2? ? ? ? ? 0 3? ? ? ? ? 0 4? ? ? ? ? 0 5 ready/busy ready/busy 1 ready/busy ready/busy 1 ready/busy 0 = busy 1 = ready 6 ready/busy ready/busy cache 2 ready/busy ready/busy cache 2 ready/busy 0 = busy 1 = ready 7 write protect write protect write protect write protect write protect 0 = protected 1 = not protected table 11: onfi parameters (continued) byte description value free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 35 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary figure 24: status register operation 70h ce# cle we# re# i/ox status output t rea t clr free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 36 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary program operations program page 80h-10h micron nand flash devices are inherently page-programmed devices. pages must be programmed consecutively within a block, fr om the least significant page address to most significant page address (i.e., 0, 1, 2, ?, 63). random page address programming is prohibited. micron nand flash devices also support partial-page programming operations. this means that any single bit can only be programmed one time before an erase is required; however, the page can be partitioned such that a maximum of four programming opera- tions are supported before an erase is required. serial data input 80h program page operations require loading the serial data input (80h) command into the command register, followed by 5 addr ess cycles, then the data. serial data is loaded on consecutive we# cycles starting at the given address. the program (10h) command is written after the data input is complete. the control logic automatically executes the proper algorithm and controls all the necessary timing to program and ver- ify the operation. write verification only detects ?1s? that are not successfully written to ?0s.? r/b# goes low for the duration of array programming time, t prog. the read status (70h) command and the reset (ffh) command are the only commands valid during the programming operation. bit 6 of the status re gister will reflect the state of r/b#. when the device reaches ready, read bit 0 of the status register to determine if the program operation passed or failed (see figure 25). th e command register st ays in read status register mode until another va lid command is written to it. random data input 85h after the initial data set is input, additional data can be written to a new column address with the random data input (85h) command. the random data input com- mand can be used any number of times in the same page prior to issuing the page write (10h) command. see figures 25 for the proper command sequence. figure 25: program and read status operation figure 26: random data input i/ox 80h address (5 cycles) 10h 70h r/b# t prog status i/o 0 = 0 program successful i/o 0 = 1 program error d in i/ox 80h address (5 cycles) 85h address (2 cycles) 10h r/b# t prog d in d in status 70h free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 37 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary program page cache mode 80h-15h cache programming is actually a buffered programming mode of the standard pro- gram page command. programming is started by loading the serial data input (80h) command to the command register, followed by 5 cycles of address, and a full or partial page of data. the data is initially copied into the cache register, and the cache program (15h) command is then latched to the command register. data is transferred from the cache register to the data register on the rising edge of we#. r/b# goes low during this transfer time. after the data has been copied into the data register and r/b# returns to high, memory array programming begins. when r/b# returns to high, new data can be written to the cache register by issuing another cache program command sequence. th e time that r/b# stays low will be controlled by the actual programming time. the first time through equals the time it takes to transfer the cache register contents to the data register. on the second and sub- sequent programming passes, transfer from the ca che register to the data register is held off until current data register content has been programmed into the array. the program page cache mode command can cross block address boundaries. random data input (85h) commands are permitted with program page cache mode operations. bit 6 (cache r/b#) of the status register can be read by issuing the read status (70h) command to determine when the cache register is ready to accept new data. the r/b# pin always follows bit 6. bit 5 (r/b#) of the status register can be polled to determine when the actual program- ming of the array is complete for the current programming cycle. if just the r/b# pin is used to determine programming completion, the last page of the program sequence must use the program page (10h) command instead of the cache program (15h) command. if the cache program (15h) command is used every time, including the last page of the programmi ng sequence, status register bit 5 must be used to determine when programming is complete (see figure 27 on page 37). bit 1 of the status register returns the pass/f ail for the previous page when bit 6 of the status register is a ?1? (ready state). the pass/fail status of the current program opera- tion is returned with bit 0 of the status regist er when bit 5 of the status register is a ?1? (ready state) as shown in figure 27 on page 37. figure 27: program page cache mode example notes: 1. see note 3, table 32 on page 70. 2. check i/o[6:5] for inte rnal ready/busy. check i/o[1:0] fo r pass/fail status. re# can stay low or pulse multiple times after a 70h command. t cbsy r/b# i/ox r/b# i/ox address & data input 80h 15h address & data input 80h 15h address & data input 80h 15h address & data input 80h 10h t cbsy t cbsy t lprog 1 t cbsy address & data input 80h 15h address & data input 80h 10h status output 2 70h t lprog 1 status output 2 70h a: without status reads b: with status reads free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 38 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary internal data move an internal data move requires two comm and sequences. issue a read for internal data move (00h-35h) command first, then the program for internal data move (85h-10h) command. read for internal data move 00h-35h the read for internal data move (00h-35h) command is used in conjunction with the program for internal data move (85h-10h) command. first, 00h is written to the command register, then the internal source address is written (5 cycles). after the address is input, the read for internal data move (35h) command writes to the command register. this transfers a page from memory into the cache register. all 5 address cycles are required when a read for internal data move command is issued. after a read for internal data move (00h-35h) command is issued and r/b# returns high, signifying operation completio n, the data transferred from the source page into the cache register may be read out by toggling re#. data is output sequentially from the column address originally specified with the read for internal data move (00h-35h) command. random data read (05h-e0h) commands can be issued without limit after the read for internal data move command. the memory device is now ready to accept the program for internal data move command. please refer to the description of this command in the following section. program for internal data move 85h-10h after the read for internal data move (00h-35h) command has been issued and r/b# goes high, the program for internal data move (85h-10h) command can be written to the command register. this command transfers the data from the cache register to the data register and programming of the new destination page begins. the sequence: 85h, destination address (5 cycles), then 10h, is written to the device. after 10h is written, r/b# goes low while the control logic automatically programs the new page. the read status command can be used instead of the r/b# line to determine when the write is complete. when status register bit 6 = 1, bit 0 of the status register indicates if the opera- tion was successful. the random data input (85h) command can be used during the program for internal data move command sequence to modify one or more bytes of the original data. first, data is copied into the cache register using the 00h-35h command sequence, then the random data input (85h) command is written along with the address of the data to be modified next. new data is input on the external data pins. this copies the new data into the cache register. when 10h is written to the command register, the original data plus the modified data are transferred to the data register, and programming of the new page is started. the random data input command can be issued as many times as necessary before starting the programming sequence with 10h (see figures 28 and 29 on page 39). because internal data move operations do not use external memory, ecc cannot be used to check for errors before programming the data to a new page. this can lead to a data error if the source page contains a bit error due to charge loss or charge gain. in the case that multiple internal data mo ve operations are performed, these bit errors may accumulate without correction. for this reason, it is highly recommended that systems using internal data move operations also use a robust ecc scheme that can correct 2 or more bits per sector. free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fmrev. a 8/08 en 39 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary figure 28: internal data move figure 29: internal data move with optional random data output and random data input optional r/b# re# we# i/ox t r t prog data output status address (5 cycles) 85h 10h unlimited number of repetitions 70h address (5 cycles) address (2 cycles) data output 35h 05h e0h 00h optional t r address (2 cycles) status data 10h 85h t prog unlimited number of repetitions 70h 00h address (5 cycles) data output 35h r/b# re# we# i/ox address (5 cycles) data 85h free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 40 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary block erase operation block erase 60h - d0h erasing occurs at the block level. for example, the mt29f2g08abd device has 2,048 erase blocks, organized into 64 pages per block, 2,112 bytes per page (2,048 + 64 bytes). each block is 132k bytes (1 28k + 4k bytes). the block erase command operates on one block at a time (see figure 30). three cycles of addresses ba[18:6] and pa[5:0] are required. although page addresses pa[5:0] are loaded, they are a ?don?t care? and are ignored for block erase operations. see table 4 on page 16 for addressing details. the actual command sequence is a two-st ep process. the erase setup (60h) com- mand is first written to the command register . then 3 cycles of addresses are written to the device. next, the erase confirm (d0h) command is written to the command reg- ister. at the rising edge of we#, r/b# goes low and the control logic automatically con- trols the timing and erase-verify oper ations. r/b# stays low for the entire t bers erase time. the read status (70h) command can be used to check the status of the block erase operation. when bit 6 = 1, the erase operation is complete. bit 0 indicates a pass/fail condition where 0 = pass (see figure 30, and table 12 on page 34). figure 30: block erase operation notes: 1. i/o[15:8] is applicable only for x16 devices. 2. invert area bit is applicable for 24h co mmand; it may be low or high for 23h command. re# ce# ale cle i/ox 60h address input (3 cycles) status d0h 70h r/b# we# t bers dont care i/o 0 = 0 erase successful i/o 0 = 1 erase error free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 41 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary block lock feature the block lock feature of this nand flash device provides the ability to protect the entire device or ranges of blocks from program and erase operations. using this block lock feature offers increased functional ity and flexibility over using just the wp# pin to prevent program and erase operations. block lock features are enabled and disabled at power-on through the use of the lock pin. at power-on, if lock is low, all bl ock lock commands are disabled. however, at power-on, if lock is high, the block lock co mmands are enabled and, by default, all of the blocks on the device are protected, or locked, from program and erase opera- tions, even if wp# is high. before the contents of the device can be modified, the device must first be unlocked. either a range of blocks or the entire device may be unlocked. program and erase operations complete successfully only in the block ranges that have been unlocked. blocks, once unlocked, can be locked again to protect them from further program and erase operations. blocks that are locked can be protected furthe r, or locked tight. when locked tight, the device?s blocks can no longer be locked or unlocked until the device is power cycled. wp# and block lock ? holding wp# low locks all blocks provided the blocks are not locked tight. ? if wp# is held low to lock blocks, then returned to high, a new unlock command must be issued to unlock blocks. unlock 23h-24h by default at power-on if lock is high, all of the blocks in the nand flash device are locked, meaning that they are protected from program and erase operations. the unlock (23h) command is used to unlock a range of blocks. unlocked blocks have no protection and can be programmed or erased. the unlock command uses two registers, a lower boundary block address register and an upper boundary block address register, and the invert area bit to determine what range of blocks are unlocked. when the invert area bit = 0, the range of blocks within the lower and upper boundary address registers are unlocked. when the invert area bit = 1, the range of blocks outside the boundaries of the lower and upper boundary address registers are unlocked. the lower boundary block address must be less than the upper boundary block address. figures 31 and 32 on page 42 show examples of how the lower and upper boundary address registers work with the invert area bit. to unlock a range of blocks, issue the unlock (23h) command followed by the appro- priate address cycles that indicate the lo wer boundary block address. then issue the 24h command followed by the appropriate address cycles that indicate the upper boundary block address. the least significant page address bit, pa0, should be set to ?1? if setting the invert area bit; otherwise, it should be ?0.? the other page address bits should be ?0? (see figure 33 on page 43). only one range of blocks can be specified in the lower and upper boundary block address registers. if after unlocking a rang e of blocks the unlock command is again issued, the new block address range determines which blocks are unlocked. the previ- ous unlocked block address range is not retained. free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 42 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary figure 31: flash array protected: inverted area bit = 0 figure 32: flash array protected: invert area bit = 1 notes: 1. i/o[15:8] is applicable only for x16 devices. 2. invert area bit is applicable for 24h co mmand; it may be low or high for 23h command. table 13: block lock address cycle assignments ale cycle i/o[15:8] 1 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first low ba7 ba6 low low low low low invert area bit 2 second low ba15ba14ba13ba12ba11ba10 ba9 ba8 third low low low low low low low ba17 ba16 block 2047 block 2046 block 2045 block 2044 block 2043 block 2042 block 2041 block 2040 block 2039 . . . . . . . . . . . . . . block 0002 block 0001 block 0000 ffch ff8h unprotected area protected area protected area upper block boundary lower block boundary ffch ff8h protected area upper block boundary lower block boundary unprotected area unprotected area block 2047 block 2046 block 2045 block 2044 block 2043 block 2042 block 2041 block 2040 block 2039 . . . . . . . . . . . . . . block 0002 block 0001 block 0000 free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 43 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary figure 33: unlock operation lock 2ah by default at power-on, if lock is high, all of the blocks in the nand flash device are locked, meaning that they are protected fr om program and erase operations. if por- tions of the device are unlocked using the unlock (23h) command, they can be locked again using the lock (2ah) command. the lock command locks all of the blocks in the device. locked blocks are write-protected from program and erase operations. to lock all of the blocks in the device, issue the lock (2ah) command. when a program or erase operation is issu ed to a locked block, r/b# goes low for t lbsy. the program or erase operation does not complete. any read status com- mand reports bit 7 as ?0,? indicating that the block is protected. the lock (2ah) command is disabled if lock is low at power-on or if the device is locked tight (see ?lock-tight 2ch? on page 44). figure 34: lock operation unlock lower boundary upper boundary cle ce# we# ale re# wp# i/ox r/b# 23h 24h block add 1 block add 2 block add 3 block add 1 block add 2 block add 3 lock command cle ce# we# i/ox 2ah free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 44 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary lock-tight 2ch the lock-tight (2ch) command prevents locked blocks from being unlocked and also prevents unlocked blocks from being locked. when this command is issued, the unlock (23h) and lock (2ah) commands are disabled. this provid es an additional level of protection agains t inadvertent program and erase operations to locked blocks. to implement lock-tight in all of the locked bl ocks in the device, verify that wp# is high and then issue the lock-tight (2ch) command. when a program or erase operation is issued to a locked block that has also been locked tight, r/b# goes low for t lbsy. the program or erase operation does not complete. the read status (70h) command reports bit 7 as ?0,? indicating that the block is protected. program and erase oper ations complete successfully to blocks that were not locked at the time the lock-tight command was issued. after the lock-tight command is issued, the command cannot be disabled via a soft- ware command. the only ways to disable the lock-tight status is to power cycle the device. when the lock-tight status is disabled , all of the blocks be come locked, the same as if the lock (2ah) command had been issued. the lock-tight (2ch) command is disabled if lock is low at power-on. figure 35: lock-tight operation lock-tight command lock wp# cle ce# we# i/ox r/b# 2ch dont care free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 45 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary figure 36: program/erase issued to locked block r/b# i/ox program or erase address/data input confirm 70h 60h t lbsy locked block read status free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 46 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary block lock read status 7ah the block lock read status (7ah) command is used to determine the protection status of individual blocks. the address cy cles have the same format as shown in table 14; the invert area bit should be set low. on the falling edge of re# the i/o pins output the block lock status register which contains the information on the protection status of the block. table 14 shows how to in terpret the block lock status register bits. figure 37: block lock read status table 14: block lock status register bit definitions block lock status register definitions i/o[7:3] i/o2 (lock#) i/o1 (lt#) i/o0 (lt) block is locked-tight x001 block is locked x010 block is unlocked, and device is locked-tight x101 block is unlocked, and device is not locked-tight x110 block lock read status block address cle ce# we# ale re# i/ox 7ah add 1 add 2 add 3 status t whr free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 47 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary figure 38: block lock flow chart power-up power-up with lock high lock-tight cmd with lock high lock-tight cmd with lock high lock-tight cmd with lock high unlock cmd with invert area bit = 1 lock cmd lock cmd unlock cmd with invert area bit = 0 unlock cmd with invert area bit = 0 unlock cmd with invert area bit = 1 unlock cmd with invert area bit = 1 unlock cmd with invert area bit = 0 entire nand flash array locked entire nand flash array locked tight block lock function disabled unlocked range locked range unlocked range unlocked range locked-tight range unlocked range locked-tight range unlocked range locked-tight range power-up with lock low (default) locked range unlocked range locked range free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 48 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary one-time programmable (otp) area this micron nand flash device offers a protected, one-time programmable nand flash memory area. ten full pages (2,112 bytes per page) of otp data is available on the device, and the entire range is guaranteed to be good. the otp area is accessible only through the otp commands. customers can use the otp area in any way they desire; typical uses include programming serial nu mbers or other data for permanent storage. in micron nand flash devices, the otp area le aves the factory in a non-written state (all bits are ?1s?). programming or partial-page programming enables the user to program only ?0? bits in the otp area. the otp area cannot be erased, even if it is not protected. protecting the otp area simply prevents further programming of the otp area. while the otp area is referred to as ?one-time programmable,? micron provides a unique way to program and verify data?bef ore permanently protecting it and prevent- ing future changes. otp programming and protection are accompli shed in two discrete operations. first, using the otp data program (a0h-10h) command, an otp page is programmed entirely in one operation, or in up to fo ur partial-page progra mming sequences. pro- gramming can occur on other pages within the otp area in a similar manner. second, the otp area is permanently protected from further programming using the otp data protect (a5h-10h) command. the pages within the otp area can always be read using the otp data read (afh-30h) command, whether or not it is protected. to determine whether or not the device is bu sy during an otp operation, either monitor r/b# or use the read status (70h) command. otp data program a0h-10h the otp data program (a0h-10h) command is used to write data to the pages within the otp area. an entire page can be programmed at one time, or a page can be partially programmed up to four times. there is no erase operation for the otp pages. the otp data program command allows programming into an offset of an otp page, using the 2 bytes of column address (ca[11:0] fo r x8 devices or ca[10:0] for x16 devices). the otp data program command will not execute if the otp area has been pro- tected. to use the otp data program command, issue the a0h command. issue 5 address cycles: the first 2 address cycles are the column address, and for the remaining 3 cycles select a page in the range of 02h-00h-00h through 0bh-00h-00h. next, write from 1 to 2,112 bytes of data. after data input is complete, issue the 10h command. the internal control logic automatically executes the pr oper programming algorithm and controls the necessary timing for programming and verification. program verification only detects ?1s? that are not successfully written to ?0s.? r/b# goes low during the duration of the array programming time ( t prog). the read status (70h) command is the only comma nd valid during the otp data program operation. bit 5 of the status register will reflec t the state of r/b#. if bit 7 is ?0,? then the otp area has been protected; otherwise, it will be a ?1.? when the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see table 12 on page 34). it is possible to program each otp page a maximum of four times. free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 49 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary random data input 85h after the initial otp data set is input, additional data can be written to a new column address with the random data input (85h) command. the random data input command can be used any number of times in the same page prior to issuance of the otp page write (10h) command. see figure 40 for the proper command sequence. figure 39: otp data program notes: 1. the otp page must be within the 02h?0bh range. we# ce# ale cle re# r/b# i/ox dont care otp data written (following "good" status confirmation) t wc t wb t prog otp data input command program command read status command 1 up to m bytes serial input a0h col add 1 col add 2 d in n d in m 00h 00h 10h 70h status otp page 1 free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fmrev. a 8/08 en 50 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary figure 40: otp program with random data input we# ce# ale cle re# r/b# i/ox dont care otp data written (following "good" status confirmation) t wc t wb t prog otp data input command program command read status command 1 up to m bytes serial input a0h col add 1 col add 2 d in n d in m 00h 00h 70h 1 status otp page 1 random data input command new column address in selected otp page 85h col add 1 d in p col add 2 10h d in q free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 51 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary otp data protect a5h-10h the otp data protect (a5h-10h) command is used to protect all the data in the otp area. after the data is protected it cannot be programmed further. when the otp area is protected, the pages within the area are no longer programmable and cannot be unpro- tected. to use the otp data protect command, issue the a5h command. next, issue the fol- lowing 5 address cycles: 00h-00h-01h-00h-00h. finally, issue the 10h command. r/b# goes low while the otp area is being protected. the protect command duration is similar to a normal page programming operation, t prog. the read status (70h) com- mand is the only command valid during the otp data protect operation. bit 5 of the status register will reflect the state of r/b#. when the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see table 12 on page 34). figure 41: otp data protect notes: 1. otp data is protected foll owing ?good? status confirmation. we# ce# ale cle re# r/b# i/ox dont care t wc t wb t prog otp data protect command otp data protected 1 program command read status command a5h col 00h col 00h 10h 70h status 01h 00h 00h free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 52 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary otp data read afh-30h the otp data read (afh-30h) command is used to read data from a page within the otp area. an otp page within the otp area is available for reading data whether or not the area is protected. to use the otp data read command, issue the afh command. next, issue 5 address cycles: the first 2 address cycles are the column address, and for the remaining 3 cycles select a page in the range of 02h-00h-00h through 0bh-00h-00h. finally, issue the 30h command. r/b# goes low ( t r) while the data is moved from the otp page to the data register. the read status (70h) command and the reset (ffh) command are the only commands valid during the otp data read operation. bi t 5 of the status register will reflect the state of r/b#. for details, refer to table 12 on page 34. normal read operation timings apply to otp read accesses (see figure 42). additional pages within the otp area can be selected by repeating the otp data read command. the random data read command enables the user to specify a new column address within the otp page so the data at single or multiple column addresses can be read. the random read mode is enabled after a no rmal otp data read (afh-30h) sequence. random data can be output after the initial page read by writing an 05h-e0h command sequence along with the new column address (2 cycles). the random data read command can be issued without limit within the otp page. only data on the current page can be read. pulsing the re# pin outputs data sequentially (see figure 43 on page 53). figure 42: otp data read operation notes: 1. the otp page must be within the 02h?0bh range. we# ce# ale cle re# r/b# i/ox busy t r d out n d out n + 1 d out m afh 00h 00h 30h dont care otp page 1 col add 2 col add 1 free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fmrev. a 8/08 en 53 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary figure 43: otp data read with random data read notes: 1. the otp page must be within the range 02h?0bh. we# ce# ale cle re# r/b# i/ox busy t r d out n d out n + 1 d out m afh 00h 00h 30h col add 1 col add 2 dont care otp page 1 05h col add 1 d out h d out p col add 2 e0h free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 54 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary features operations the get features (eeh) and set features (efh) commands are used to alter the nand flash device behavior from the default power-on behavior. these commands use a 1-byte feature address to determine which fe ature is to be read or modified. each fea- ture (in the range of 0 to 255) is defined in the features table (table 15). the get fea- tures (eeh) command (see ?get features eeh? on page 56) simply reads the parameter in the features table (4 bytes). the set features (efh) command (see ?set features efh? on page 57) places parame ters in the features table (4 bytes). when a feature is set, by default it remains active until the device is power-cycled. it is volatile. unless otherwise specified in the features table, once a device is set it remains set, even if a reset (f fh) command is issued. notes: 1. the timing-mode feature address is used to change the default ti ming mode. the timing mode should be selected to indicate the maximum speed at which the device will receive commands, addresses, and data cycles. the five supported settings fo r the timing mode are shown. the default timing mode is mode 0. the device returns to mode 0 when the device is power cycled. supported timing mode s are reported in the parameter page. 2. supported for both 1.8v and 3.3v. 3. supported for 3.3v only. 4. not supported. table 15: features feature address description 00h n/a 01h timing mode 02h?7fh reserved 80h vendor-specific parameter: pr ogrammable i/o drive strength 81h vendor-specific parameter: progra mmable r/b# pull-down strength 82h-ffh reserved table 16: feature address 01h: timing mode subfeature parameter options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value notes p1 timing mode mode 0 (default) reserved (0) 0 0 0 00h 1,2 mode 1 reserved (0) 0 0 1 01h 2 mode 2 reserved (0) 0 1 0 01h 3 mode 3 reserved (0) 0 1 1 01h 3 mode 4 reserved (0) 1 0 0 01h 3 mode 5 reserved (0) 1 0 1 01h 4 p2 reserved (0) 00h p3 reserved (0) 00h p4 reserved (0) 00h free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 55 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary notes: 1. the programmable drive strength featur e address is used to change the default i/o drive strength. drive strength should be sele cted based on expected loading of the mem- ory bus. this table shows the four supported output drive-st rength settings. the default drive strength is full strength. the device re turns to the default drive strength mode when the device is power cycled. ac timing parameters may need to be relaxed if i/o drive strength is not set to full. notes: 1. the programmable r/b# pull-down strength feature address is used to change the default r/b# pull-down strength. r/b# pull-down stren gth should be selected based on expected loading of r/b#. the four supported pull-down strength settings are shown. the default pull-down strength is full strength. the devi ce returns to the defa ult pull-down strength when the device is power cycled. table 17: feature address 80h: programmable i/o drive strength subfeature parameter options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value notes p1 i/o drive strength full (default) reserved (0) 0 0 00h 1 three-quarters reserved (0) 0 1 01h one-half reserved (0) 1 0 02h one-quarter reserved (0) 1 1 03h p2 reserved (0) 00h p3 reserved (0) 00h p4 reserved (0) 00h table 18: feature address 81h: programmable r/b# pull-down strength subfeature parameter options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value notes p1 r/b# pull-down strength full (default) reserved (0) 0 0 00h 1 three-quarters reserved (0) 0 1 01h one-half reserved (0) 1 0 02h one-quarter reserved (0) 1 1 03h p2 reserved (0) 00h p3 reserved (0) 00h p4 reserved (0) 00h free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 56 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary get features eeh the get features command is used to determine the current settings for the specified feature address. this command returns the parameter settings, including modifications made previously with the set features function. figure 44 defines get features behavior and timing. figure 44: get features (eeh) notes: 1. p1?p4 are the parameters for the specified feature address (fa). we# ce# ale cle re# i/ox feature address, 1 cycle eeh fa p3 p1 1 p2 p4 t feat r/b# free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 57 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary set features efh the set features command is used to set the parameters at a specified feature address. these parameters are stored in the device until power is cycled. they are applied to all die on the ce# to which this command is issued. figure 45: set features (efh) notes: 1. p1?p4 are the parameters for the specified feature address (fa). we# ce# ale cle re# i/ox feature address, 1 cycle efh fa p3 p1 1 p2 p4 t feat r/b# free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 58 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary reset operation reset ffh the reset command is used to put the memory device into a known condition and to abort the command sequence in progress. read, program, and erase commands can be aborted while the device is in the busy state. the contents of the memory location being programmed or the block being erased are no longer valid. the data may be partiall y erased or programmed, and is invalid. the command register is cleared and is ready for the next command. the data register and cache register contents are marked invalid. the status register contains the value e0h when wp# is high; otherwise it is written with a 60h value. r/b# goes low for t rst after the reset command is written to the command register (see figure 46 and table 19). the reset command must be issued to all ce#s as the first command after power-on. the device will be busy for a maximum of 1ms. figure 46: reset operation table 19: status register contents after reset operation condition status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex wp# high ready 11100000e0h wp# low ready and write protected 0110000060h cle ce# we# r/b# i/ox t rst t wb ffh reset command free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 59 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary write protect operation it is possible to enable and disable pr ogram and erase commands using the wp# pin. figures 47 through 50 illu strate the setup time ( t ww) required from wp# toggling until a program or erase command is latched in to the command register. after command cycle 1 is latched, the wp# pin must not be toggled until the command is complete and the device is ready (status register bit 5 is ?1?). figure 47: erase enable figure 48: erase disable figure 49: program enable t ww 60h d0h we# i/ox wp# r/b# t ww 60h d0h we# i/ox wp# r/b# t ww 80h 10h (or 15h) we# i/ox wp# r/b# free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 60 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory command definitions micron confidential and proprietary figure 50: program disable figure 51: program for internal data move enable figure 52: program for internal data move disable t ww 80h 10h (or 15h) we# i/ox wp# r/b# t ww 85h 10h we# i/ox wp# r/b# t ww 85h 10h we# i/ox wp# r/b# free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 61 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory error management micron confidential and proprietary error management this nand flash device is specified to have the minimum number of valid blocks (n vb ) of the total available blocks per die shown in table 20. this means the devices may have blocks that are invalid when shipped from the factory. an invalid block is one that con- tains at least one page that has more bad bi ts than can be corrected by the minimum required ecc. additional bad blocks may de velop with use. however, the total number of available blocks will not fall below n vb during the endurance life of the product. although nand flash memory devices may contain bad blocks, they can be used reli- ably in systems that provide bad-block management and error-correction algorithms. this ensures data integrity. internal circuitry isolates ea ch block from other blocks, so the presence of a bad block does not affect the operation of the rest of the nand flash array. nand flash devices are shipped from the factory erased. the factory identifies invalid blocks before shipping by attempting to pr ogram the bad-block mark into every location in the first page of each invalid block. it may not be possible to program every location in an invalid block with the bad-block mark. however, the first spare area location in each bad block is guaranteed to contain the bad- block mark. this method is compliant with onfi factory defect mapping requirements. see table 20 for the bad-block mark. system software should initially check the fi rst spare area location for non-ffh data on the first page of each block prior to perfor ming any program or erase operations on the nand flash device. a bad-block table can then be created, enabling system software to map around these areas. factory testing is performed under worst-case conditions. because invalid blocks may be marginal, it may not be possible to recover the bad-block marking if the block is erased. over time, some memory locations may fail to program or erase properly. in order to ensure that data is stored properly over the life of the nand flash device, the following precautions are required: ? check status after each program and erase operation. ? under typical conditions, use the minimum required ecc shown in table 20. ? use bad-block management an d wear-leveling algorithms. the first block (physical block address 00h) for each ce# is guaranteed to be valid with ecc when shipped from the factory. table 20: error management details description requirement minimum number of valid blocks (n vb )2,008 total available blocks per die 2,048 minimum required ecc 1-bit ecc per 528 bytes of data first spare area location x8: byte 2,048 x16: word 1,024 bad-block mark x8: 00h x16: 0000h free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 62 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory electrical characteristics micron confidential and proprietary electrical characteristics stresses greater than those listed under ?absolute maximum ratings? may cause perma- nent damage to the device. this is a stress rating only , and functional operation of the device at these or any other conditions abov e those indicated in the operational sections of this specification is not guaranteed. exposure to absolute maximum rating conditions for extended periods ma y affect reliability. table 21: absolute maximum ratings voltage on any pin relative to v ss parameter/condition symbol min max unit voltage input 3.3v v in ?0.6 +4.6 v voltage input 1.8v v in ?0.6 +2.4 v v cc supply voltage 3.3v v cc ?0.6 +4.6 v v cc supply voltage 1.8v v cc ?0.6 +2.4 v storage temperature t stg ?65 +150 c short circuit output current, i/os ?5ma table 22: recommended operating conditions parameter/condition symbol min typ max unit operating temperature t a 0 ? +70 c extended temperature ?40 ? +85 c v cc supply voltage v cc 2.7 3.3 3.6 v v cc supply voltage v cc 1.65 1.8 1.95 v ground supply voltage v ss 000v free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 63 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory electrical characteristics micron confidential and proprietary v cc power cycling micron nand flash devices are designed to prevent data corruption during power tran- sitions. v cc is internally monitored. (the wp# signal permits additional hardware pro- tection during power transitions.) when v cc reaches 2.5v for a 3.3v device or 1.5v for a 1.8v device, a minimum of 100s should be al lowed for the flash device to initialize before any commands are executed (see figu res 53 for the states of signals during v cc power cycling). both of the following conditions must be satisfied before r/b# will be valid: ? 50s have elapsed since vcc started its ramp. ? 10s have elapsed since vcc reached 2.5v for 3.3v or 1.5v for 1.8v the reset command must be issued to all ce#s as the first command after the nand flash device is powered on. each ce# will be busy for a maximum of 1ms after a reset command is issued. each nand die will draw no more than i st prior to execution of the first reset com- mand after the device is powered on. figure 53: ac waveforms during power transitions 100s (min) undefined dont care ffh 1ms (max) 10s (max) 50s (max) t cs v cc cle ce# wp# we# ale re# i/ox r/b# 3v device: 2.5v 1.8v device: 1.5v 3v device: 2.5v 1.8v device: 1.5v free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 64 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory electrical characteristics micron confidential and proprietary notes: 1. v oh and v ol may need to be relaxed if i/o dr ive strength is not set to ?full.? 2. i ol (rb#) may need to be relaxed if r/b pull-down strength is not set to ?full.? 3. measurement is taken with 1ms averaging intervals and begins after vcc reaches vcc (min). table 23: dc and operating characteristics (3.3v) parameter conditions symbol min typ max unit notes sequential read current t rc = t rc (min); ce# = v il ; i out = 0ma i cc 1 ? 25 35 ma program current ?i cc 2 ? 25 35 ma erase current ?i cc 3 ? 25 35 ma standby current (ttl) ce# = v ih ; wp# = 0v/v cc i sb 1? ? 1ma standby current (cmos) ce# = v cc - 0.2v; wp# = 0v/v cc i sb 2 ? 10 50 a staggered power-up current 3 rise time = 1ms line capacitance = 0.1f i st ??10 per diema3 input leakage current v in = 0v to v cc i li ? ? 10 a output leakage current v out = 0v to v cc i lo ? ? 10 a input high voltage i/o[7:0], i/o[15:0], ce#, cle, ale, we#, re#, wp#, r/b# v ih 0.8 x v cc ?v cc + 0.3 v input low voltage, all inputs ?v il ?0.3 ? 0.2 x v cc v output high voltage i oh = ?400a v oh 2.4 ? ? v 1 output low voltage i ol = 2.1ma v ol ??0.4v1 output low current v ol = 0.4v i ol (r/b#) 8 10 ? ma 2 free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 65 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory electrical characteristics micron confidential and proprietary table 24: dc and operating characteristics (1.8v) notes: 1. v oh and v ol may need to be relaxed if i/o dr ive strength is not set to ?full.? 2. i ol (rb#) may need to be relaxed if r/b pull-down strength is not set to ?full.? 3. measurement is taken with 1ms averaging intervals and begins after vcc reaches vcc (min). parameter conditions symbol min typ max unit notes sequential read current t rc = t rc (min); ce# = v il ; i out = 0ma i cc 1 ? 10 20 ma program current ?i cc 2 ? 10 20 ma erase current ?i cc 3 ? 10 20 ma standby current (ttl) ce# = v ih ; lock = wp# = 0v/v cc i sb 1? ? 1ma standby current (cmos) ce# = v cc - 0.2v; lock = wp# = 0v/v cc i sb 2 ? 10 50 a staggered power-up current 3 rise time = 1ms line capacitance = 0.1f i st ??10 per diema3 input leakage current v in = 0v to v cc i li ? ? 10 a output leakage current v out = 0v to v cc i lo ? ? 10 a input high voltage i/o[7:0], i/o[15:0], ce#, cle, ale, we#, re#, wp#, r/b#, lock v ih 0.8 x v cc ?v cc + 0.3 v input low voltage, all inputs ?v il ?0.3 ? 0.2 x v cc v output high voltage i oh = ?100a v oh v cc - 0.1 ? ? v 1 output low voltage i ol = 100a v ol ??0.1v1 output low current v ol = 0.2v i ol (r/b#) 3 4 ? ma 2 free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 66 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory electrical characteristics micron confidential and proprietary notes: 1. invalid blocks are blocks that contain on e or more bad bits. the device may contain bad blocks upon shipment. additional bad blocks may develop over time; however, the total number of available blocks will not drop below n vb during the endurance life of the device. do not erase or program bloc ks marked invalid by the factory. 2. block 00h (the first block) is guaranteed to be valid with ecc wh en shipped from the fac- tory. notes: 1. these parameters are verified in device characterization and are not 100 percent tested. 2. test conditions: t c = 25c; f = 1 mhz; v in = 0v. notes: 1. verified in device charac terization, not 100 percent tested. table 25: valid blocks parameter symbol device min max unit notes valid block number n vb mt29f2gxxaxd 2,008 2,048 blocks 1, 2 table 26: capacitance description symbol max unit notes input capacitance c in 10 pf 1,2 input/output capacitance (i/o) c io 10 pf 1.2 table 27: test conditions parameter device value notes input pulse levels mt29f2gxxaxd 0.0v to v cc input rise and fall times 5ns input and output timing levels v cc /2 output load 3.3v 1 ttl gate and cl = 50pf 1 1.8v 1 ttl gate and cl = 30pf 1 free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 67 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory electrical characteristics micron confidential and proprietary notes: 1. timing for begins t adl begins in the address cycle on the final rising edge of we# and ends with the first rising edge of we# for data input. notes: 1. timing for begins t adl begins in the address cycle on the final rising edge of we# and ends with the first rising edge of we# for data input. table 28: ac characteristics: command, data, and address input (3.3v) parameter symbol min max unit notes ale to data start t adl 70 ? ns 1 ale hold time t alh 5?ns ale to setup time t als 10 ? ns ce# hold time t ch 5?ns cle hold time t clh 5?ns cle setup time t cls 10 ? ns ce# setup time t cs 15 ? ns data hold time t dh 5?ns data setup time t ds 10 ? ns write cycle time t wc 25 ? ns we# pulse width high t wh 10 ? ns we# pulse width t wp 12 ? ns wp# setup time t ww 100 ? ns table 29: ac characteristics: command, data, and address input (1.8 v) parameter symbol min max unit notes ale to data start t adl 100 ? ns 1 ale hold time t alh 4?ns ale setup time t als 15 ? ns ce# hold time t ch 4?ns cle hold time t clh 5?ns cle setup time t cls 15 ? ns ce# setup time t cs 24 ? ns data hold time t dh 4?ns data setup time t ds 15 ? ns write cycle time t wc 35 ? ns we# pulse width high t wh 15 ? ns we# pulse width t wp 17 ? ns wp# setup time t ww 100 ? ns free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 68 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory electrical characteristics micron confidential and proprietary notes: 1. ac characteristics may need to be relaxe d if i/o drive strength is not set to ?full.? 2. transition is measured 200mv from steady-sta te voltage with load. this parameter is sam- pled and not 100 percent tested. 3. the first time the reset (ffh) co mmand is issued while the device is idle, the device will go busy for a maximum of 1ms. thereafter, the device goes bu sy for maximum 5s. 4. do not issue a ne w command during t wb, even if r/b# is ready. table 30: ac characteristics: normal operation (3.3v) parameter symbol min max unit notes ale to re# delay t ar 10 ? ns 1 ce# access time t cea ?25ns1 ce# high to output high-z t chz ?30ns1, 2 cle to re# delay t clr 10 ? ns 1 ce# high to output hold t coh 15 ? ns 1 cache busy in page read cache mode (first 31h) t dcbsyr1 ?3s1 cache busy in page read ca che mode (next 31h and 3fh) t dcbsyr2 t dcbsyr1 25 s 1 output high-z to re# low t ir 0?ns1 data transfer from flash array to data register t r ?25s1 read cycle time t rc 25 ? ns 1 re# access time t rea ?20ns1 re# high hold time t reh 10 ? ns 1 re# high to output hold t rhoh 15 ? ns 1 re# high to we# low t rhw 100 ? ns 1 re# high to output high-z t rhz ?100ns1, 2 re# low to output hold t rloh 5?ns1 re# pulse width t rp 12 ? ns 1 ready to re# low t rr 20 ? ns 1 reset time (read/program/erase) t rst ? 5/10/500 s 1, 3 we# high to busy t wb ?100ns1, 4 we# high to re# low t whr 60 ? ns 1 free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 69 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory electrical characteristics micron confidential and proprietary notes: 1. ac characteristics may need to be relaxe d if i/o drive strength is not set to ?full.? 2. transition is measured 200mv from steady-sta te voltage with load. this parameter is sam- pled and not 100 percent tested. 3. the first time the reset (ffh) co mmand is issued while the device is idle, the device will go busy for a maximum of 1ms. thereafter, the device goes bu sy for maximum 5s. 4. do not issue a ne w command during t wb, even if r/b# is ready. table 31: ac characteristics: normal operation (1.8v) parameter symbol min max unit notes ale to re# delay t ar 10 ? ns 1 ce# access time t cea ?30ns1 ce# high to output high-z t chz ?45ns1, 2 cle to re# delay t clr 10 ? ns 1 ce# high to output hold t coh 15 ? ns 1 cache busy in page read cache mode (first 31h) t dcbsyr1 ?3s1 cache busy in page read ca che mode (next 31h and 3fh) t dcbsyr2 t dcbsyr1 25 s 1 output high-z to re# low t ir 0?ns1 data transfer from flash array to data register t r ?25s1 read cycle time t rc 35 ? ns 1 re# access time t rea ?24ns1 re# high hold time t reh 15 ? ns 1 re# high to output hold t rhoh 15 ? ns 1 re# high to we# low t rhw 100 ? ns 1 re# high to output high-z t rhz ?100ns1, 2 re# low to output hold t rloh 0?ns1 re# pulse width t rp 17 ? ns 1 ready to re# low t rr 20 ? ns 1 reset time (read/program/erase) t rst ? 5/10/500 s 1, 3 we# high to busy t wb ?100ns1, 4 we# high to re# low t whr 80 ? ns 1 free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 70 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory electrical characteristics micron confidential and proprietary notes: 1. four total partial-page programs to the same page. 2. t cbsy max time depends on ti ming between internal prog ram completion and data-in. 3. t lprog = t prog (last page) + t prog (last - 1 page) - comman d load time (last page) - address load time (last page) - data load time (last page). table 32: program/erase characteristics symbol parameter typ max unit notes nop number of partial page programs ?4cycles1 t bers block erase operation time 0.5 3 ms t cbsy busy time for program cache operation (3.3v) 3 500 s 2 t cbsy busy time for program cache operation (1.8v) 3 600 s 2 t feat busy time for set features an d get features operations (3.3v) ?1s t feat busy time for set features an d get features operations (1.8v) ?3s t lbsy busy time for progra m/erase on locked block ?3s t lprog last page program operation time ???3 t obsy busy time for otp data program operation if otp is protected ?30s t prog page program operation time (1.8v) 300 600 s t prog page program operation time (3.3v) 220 500 s free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 71 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory timing diagrams micron confidential and proprietary timing diagrams figure 54: command latch cycle note: x16: i/o[15:8] must be set to ?0.? figure 55: address latch cycle note: x16: i/o[15:8] must be set to ?0.? we# ce# ale cle i/ox command t wp t ch t cs t alh t dh t ds t als t clh t cls dont care we# ce# ale cle i/ox col add 1 t wp t wh t cs t dh t ds t als t alh t cls col add 2 row add 1 row add 2 row add 3 dont care undefined t wc free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 72 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory timing diagrams micron confidential and proprietary figure 56: input data latch cycle notes: 1. d in final = 2,111 (x8). figure 57: serial access cycle after read note: use this timing diagram for t rc 30ns. we# ce# ale cle i/ox t wp t wp t wp t wh t als t dh t ds t dh t ds t dh t ds t clh t ch d in 1 d in final 1 dont care t wc d in 0 ce# re# i/ox t reh t rp t rr t rc t cea t rea t rea t rea dont care t rhz t chz t rhz t rhoh r/b# t coh d out d out d out free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 73 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory timing diagrams micron confidential and proprietary figure 58: serial access cycle after read (edo mode) figure 59: read status operation d out d out ce# re# i/ox r/b# t rr t cea t rea t rp t reh t rc t rloh t rea t rhoh t rhz t coh t chz dont care d out re# ce# we# cle i/ox t rhz t wp t whr t clr t ch t cls t cs t clh t dh t rp t chz t ds t rea t rhoh t ir 70h status output dont care t cea t coh free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 74 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory timing diagrams micron confidential and proprietary figure 60: page read operation d out n d out n + 1 d out m we# ce# ale cle re# r/b# i/ox t wc busy 00h 30h t r t wb t ar t rr t rp t clr t rc t rhz dont care col add 1 col add 2 row add 1 row add 2 row add 3 free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fmrev. a 8/08 en 75 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory timing diagrams micron confidential and proprietary figure 61: read operation with ce# ?don?t care? re# ce# t rea t chz t cea re# ce# ale cle i/ox i/ox out r/b# we# data output t r dont care address (5 cycles) 00h 30h t coh free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fmrev. a 8/08 en 76 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory timing diagrams micron confidential and proprietary figure 62: random data read operation we# ce# ale cle re# r/b# i/ox busy col add 1 col add 2 row add 1 row add 2 row add 3 00h t wb t ar t rr dont care t rc t rhw d out m d out m + 1 col add 1 col add 2 05h e0h t rea t clr d out n d out n + 1 30h t whr column address n column address m t r free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fmrev. a 8/08 en 77 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory timing diagrams micron confidential and proprietary figure 63: page read cache mode operation, part 1 of 2 t wc we# ce# ale cle re# r/b# i/ox column address 0 1 d out page address m page address m column address 00h t cea t ds t clh t cls t cs t ch t dh dont care t rr t wb t r t dcbsyr2 column address 0 continued to 1 of next page t rc t rea 30h d out 0 d out 0 d out 1 31h 31h col add 2 row add 1 row add 2 row add 3 00h t dcbsyr1 page address m + 1 col add 1 t rhw free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fmrev. a 8/08 en 78 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory timing diagrams micron confidential and proprietary figure 64: page read cache mode operation, part 2 of 2 we# ce# ale cle re# r/b# i/ox 1 page address m + 1 dont care page address m + 2 column address 0 continued from 1 of previous page page address m + x column address 0 t clh t ch t rea t cea t rhw t ds t dh t rr t dcbsyr2 t dcbsyr2 t wb column address 0 31h d out 0 d out 3fh d out 1 d out 0 d out d out 1 t cls t cs t rc d out 31h t dcbsyr2 t rhw d out 1 d out d out 0 free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 79 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory timing diagrams micron confidential and proprietary figure 65: page read cache mode operation without r/b#, part 1 of 2 t wc 30h 70h status d out 0 column address 0 1 d out 1 d out column address 00h page address m page address m t cea clh ch dh 31h 31h colu 70h status i/o 6 = 0, cache busy = 1, cache read i/o 5 = 0, busy = 1, ready continued to 1 of next page col add 1 col add 2 row add 1 row add 2 row add 3 h 00h 00 t rc t rea 70h status i/o 6 = 0, cache busy = 1, cache ready t rhw free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 80 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory timing diagrams micron confidential and proprietary figure 66: page read cache mode operation without r/b#, part 2 of 2 figure 67: read id operation note: see table 9 on page 30 for actual values. page address m + 1 page address m + 2 column address 0 om 1 page page m column address 0 t rea t cea t ds t dh column address 0 d out 0 d out 1 d out 31h d out 0 d out 3fh d out 1 d o 1 d out 0 t rc 31h 70h status i/o 6 = 0, cache busy = 1, cache ready 70h status i/o 6 = 0, cache busy = 1, cache ready 70h status i/o 6 = 0, cache busy = 1, cache ready 00h 00h 00h t clh t ch cls cs t rhw we# ce# ale cle re# i/ox 90h 00h (or 20h) address, 1 cycle byte 2 byte 0 byte 1 byte 3 byte 4 t ar t rea t whr free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 81 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory timing diagrams micron confidential and proprietary figure 68: program page operation figure 69: program operation with ce# ?don?t care? we# ce# ale cle re# r/b# i/ox t wc t adl serial data input command program command read status command 1 up to m byte serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n d in m 70h status 10h t prog t whr t wb dont care cle ce# we# ale i/ox address (5 cycles) data input 10h we# ce# t wp t ch t cs dont care data input 80h free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fmrev. a 8/08 en 82 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory timing diagrams micron confidential and proprietary figure 70: program page operation with random data input we# ce# ale cle re# r/b# i/ox t wc serial data input command serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n d in n+1 t adl t adl random data input command column address program command read status command serial input 85h t prog t wb t whr dont care col add 1 col add 2 d in n d in n+1 70h status 10h free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 83 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory timing diagrams micron confidential and proprietary figure 71: internal data move operation figure 72: program page cache mode operation we# ce# ale cle re# r/b# i/ox t wb t prog t wb busy busy read status t wc internal data move dont care t adl t whr col add 2 row add 1 row add 2 70h 10h status data n row add 3 col add 1 00h 35h col add 2 row add 1 row add 2 row add 3 col add 1 85h data 1 t r we# ce# ale cle re# r/b# i/ox 15h t cbsy t wb t wb t whr t lprog col add 1 80h 10h 70h status col add 2 row add 2 row add 1 col add 1 col add 2 row add 2 row add 1 row add 3 d in m d in n d in m d in n last page - 1 last page serial input t wc dont care 80h t adl row add 3 serial data input program program free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 84 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory timing diagrams micron confidential and proprietary figure 73: program page cache mode operation ending on 15h figure 74: block erase operation 15h col add 1 80h 15h 70h status 70h 70h status col add 2 row add 2 row add 1 row add 3 col dd 1 col add 2 row add 2 row add 1 row add 3 d in m d in n d in m d in n last page last page C 1 serial input program program poll status until: i/o6 = 1, ready to verify successful completio i/o5 = 1, ready i/o0 = 0, last page pro i/o1 = 0, last page C 1 p t adl t whr t w t adl we# ce# ale cle re# r/b# i/ox auto block erase setup command erase command read status command busy row address 60h row add 1 row add 2 row add 3 70h status d0h t wc t bers t wb t whr dont care i/o0 = 0, pass i/o0 = 1, fail free datasheet http:///
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks of micron technology, inc. this data sheet contains minimum and maximum limits specified ov er the power supply and temperat ure range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometime s occur. 2gb x8, x16: nand flash memory timing diagrams pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 85 ?2007 micron technology, inc. all rights reserved. micron confidential and proprietary figure 75: reset operation cle ce# we# r/b# i/ox t rst t wb ffh reset command free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 86 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory package dimensions micron confidential and proprietary package dimensions figure 76: 48-pin tsop package note: all dimensions are in millimeters. 1.20 max 0.15 +0.03 -0.02 0.27 max 0.17 min see detail a 18.40 0.08 20.00 0.25 12.00 0.08 detail a 0.50 0.1 0.80 0.10 +0.10 -0.05 0.10 0.25 gage plane 0.25 for reference only 0.50 for reference only 1 24 48 25 plated lead finish: 100% sn mold compound: epoxy novolac package width and length do not include mold protrusion. allowable protrusion is 0.25 per side. free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 87 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory package dimensions micron confidential and proprietary figure 77: 63-ball vfbga package note: all dimensions are in millimeters. ball a1 id 1.00 max mold compound: epoxy novolac substrate material: plastic laminate solder ball material: 96.5% sn, 3%ag, 0.5% cu 13.00 0.10 ball a10 ball a1 id 0.80 typ 0.80 typ 6.50 0.05 10.50 0.10 5.25 0.05 3.60 4.40 0.65 0.05 seating plane a 8.80 7.20 0.10 a ball a1 63x ?0.45 dimensions apply to solder balls post reflow. pre-reflow ball is ?0.42 on a ?0.4 smd ball pad. c l c l free datasheet http:///
pdf: 09005aef82784784 / source: 09005aef82784840 micron technology, inc., reserves the right to change products or specifications without notice. nda_2gb_nand_m59a__2.fm - rev. a 8/08 en 88 ?2007 micron technology, inc. all rights reserved. 2gb x8, x16: nand flash memory revision history micron confidential and proprietary revision history rev. a, production. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/08 ?initial release. free datasheet http:///

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